The semiconductor integrated circuit industry has experienced exponential growth. In semiconductor manufacturing, functional density is generally increasing with reduced geometry size, and smaller and more complex integrated circuits than the previous generation are produced. This scaling down process also increases the processing and manufacturing complexity of integrated circuits. For these advances to be realized, associated developments are required in the processing and manufacturing of the integrated circuits.
Usually, an integrated circuit (IC) design is formed on a wafer using various fabrication processes, such as etching, deposition, implantation, annealing, polishing and lithography. The lithography process transfers a feature from a mask to the wafer. The mask includes an IC feature and being repeatedly used in wafer fabrication, and an electron beam (e-beam) writing process is applied to fabricate the mask. As the integrated circuits are continually progressing to smaller feature sizes, e.g. 28 nanometers, 20 nanometers, or below, is the lithography processes face even more challenges to form the mask.
Various lithography processes have been approached for higher resolution such that a small feature may be precisely printed on wafers. For example, an optical proximity correction (OPC) technique is implemented in a mask fabrication. The OPC process employs a lithographic model to predict contours of the features after the lithography process. Cycle time of e-beam forming the mask is prolonged and the corresponding mask making cost is higher. Therefore, there are constant needs for a method and an apparatus for saving the mask fabricating cycle time.